A programmable logic device (PLD) is a general-purpose device that can be programmed by a user to implement a variety of selected functions. One type of PLD is the Field Programmable Gate Array (FPGA), which typically includes an array of configurable logic blocks (CLBs) surrounded by a plurality of input/output blocks (IOBs). The CLBs are individually programmable and can be configured to perform a variety of logic functions on a few input signals. The IOBs can be configured to drive output signals from the CLBs to external pins of the FPGA and/or to receive input signals from the external FPGA pins. The FPGA also includes a programmable interconnect structure that can be programmed to selectively route signals among the various CLBs and IOBs to produce more complex functions of many input signals. The CLBs, IOBs, and the programmable interconnect structure are programmed by loading configuration data into associated configuration memory cells that control various switches and multiplexers within the CLBs, IOBs, and the interconnect structure to implement logic and routing functions specified by the configuration data.
PLDs such as FPGA devices typically exhibit greater static power consumption than dedicated logic devices such as standard-cell application specific integrated circuits (ASICs). One reason for the PLD's higher power consumption is because while the PLD utilizes only a subset of its available resources for any given design, the unused resources nevertheless consume static power. As a result, PLDs have traditionally been deemed as unsuitable for low-power applications such as, for example, portable consumer electronic devices. However, continual declines in FPGA manufacturing costs has led to their deployment in high-volume portable consumer electronic devices such as PDAs, portable music players, cell phones, GPS devices, and the like. To conserve battery power, many of the components that form these portable devices are capable of entering a suspend mode that reduces static power consumption when the device or at least the component is not actively in use. It is also important for these components to quickly “wake-up” from suspend mode and return to a normal operation mode. As a result, configurable devices such as FPGAs should not be powered-down during suspend mode because all configuration data and logic states would be lost, thereby requiring a time consuming re-configuration operation.
Although there are many techniques to selectively and/or independently adjust the power provided to variously selected PLD components to reduce static power dissipation during standby mode without losing data stored in the PLD, none address the synchronization of an FPGA device to other devices in a system when the FPGA device is returning from suspend mode to active mode. For example, when an FPGA is powered-down and then re-booted in response to a system power-up, there are not any synchronization issues between the FPGA and other devices in the system because all devices are booting up and configuring themselves to pre-defined initial states. However, when the FPGA is placed in suspend mode and then returned to the active mode, the FPGA must be synchronized with the other devices in the system because one or more of the other devices may be in various states unknown to the FPGA. Further, it is also important to address the effect that an FPGA device in suspend mode may have upon the I/O buses connected between the FPGA device and other devices in the system.